The reference and VCO models have noise sources for frequency-domain and time-domain analysis. For time-domain analysis, the VCO and reference models add a Gaussian random variable to their outputs. The random variable is updated at a user-defined rate. The standard deviation of the random variable depends on the sample rate and is automatically scaled to produce the correct PSD.
The open-loop single-sided power spectral densities of all the aforementioned blocks are shown in Figure The produced phase noise plots are as expected. The time-domain simulation aids the monitoring of the settling in the phase-locked loop. Figure shows the phase-domain model time-domain simulation illustrating the voltages at each individual node in the loop. The reference frequency of 40 MHz represented here by 40 V is shown along with the feedback frequency divider output illustrating its average to 40 MHz i.
The settling of the loop is best viewed by monitoring the tuning voltage that reaches its desired value as illustrated in the figure. It can be easily seen that after It should be 54 Chapter 4 mentioned here that this simulation takes a couple of seconds compared to a few days if transistor-level transient simulations were run. In frequency-domain, open- and closed-loop phase noise can be characterized. At this level, open-loop phase noise data must be included in the phase domain model mentioned above.
Each of the individual blocks except the loop filter employs noise data derived from a phase noise mask that has been simulated and measured. The phase noise masks data obtained from Figure are incorporated in the phase model. Those can be enabled when loop phase noise is needed. All the results of individual blocks have been discussed separately above and it is time now to close the synthesizer loop by implementing initial off-chip loop filter components.
With the aid of this platform with fast simulation time, it is possible to optimize those filter components to yield optimum phase noise performance. Initial loop filter values were calculated using  and are shown in Table A snapshot of the time-domain phase model of this synthesizer in lock is shown in Figure a and b, unzoomed and zoomed, respectively.
To show the efficacy of the developed model, the synthesizer is simulated with two different loop filter bandwidths, namely kHz and 1 MHz. Figure overlays the phase noise mask for both cases.
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It could be easily demonstrated that this model correlates well with the phase noise mask for the synthesizer if linear-model control loop equations were used outside this platform. Clear observations can be summarized as follows: As the loop bandwidth is increased, the closein phase noise plateau is suppressed. These spurious signals are due to close-to-integer operation. This is due to the fact that the binary representation of such DC values has much less randomness. Figures and show the noise spectrum for 0.
Here, the spurs have been eliminated by introducing an error nonzero initial condition in the least significant bit LSB of the input word . The error is too small to affect the synthesized frequency within the permissible frequency error but is good enough to eliminate the spurs to some extent. As can be seen from Figure , there are two remnant fractional spurs seen in the region of 1 MHz. Those can be further removed by increasing the efficiency of the dithering employed. The low-frequency effect below 25 kHz is a deficiency in the power-spectral density transform function built in CadenceTM.
If low-frequency phase noise is of interest, it is advisable to export the data to a mathematical package for further accurate processing . Phase Noise Mask for the LO Synthesizer with kHz Loop Bandwidth with and without Dithering Figure shows the phase noise profile for the frequency synthesizer local oscillator at 5. Two cases are superimposed. The first case bottom trace is when no dithering is employed which shows the presence of spurious fractional content whereas the top trace is the case where dithering is applied. In this case, the spurious energy is spread across the spectrum and hence the lifting of the phase noise as illustrated in the figure.
This effect must be taken into account when designing synthesizers to strike a compromise between deterministic spurious noise and random phase noise. This becomes a problem if not catered for in advance in the design. Above, we have introduced an error to remove any fractional spurs that may arise from limit cycles.
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That error will propagate in the modulator and cause the accumulators to overflow in a determined and cyclic manner causing spurious tones for integer frequencies. For an input dc value of 0. It can be clearly seen in Figure that the modulator exhibits lowfrequency spurs due to insufficient dither.
This problem is rectified by effectively increasing the dither via introducing an initial seed  in the modulator as illustrated in Figure Figure illustrates the phase noise masks when 1-LSB and 5-LSB nonzero initial condition dithering is applied to the modulator when operating with a fractional division close to integer. With 5-LSB dithering the spurious level is reduced at the expense of lifting the phase noise level. The platform developed in this research proves this phenomenon with ease.
This is illustrated in the 10 dB deterioration of the phase noise plateau rendering the fractional-N synthesizer unattractive. Modulator Output for DC input 0. Modulator Output for DC Input 0.go
Design of PLL frequency synthesizer based on the fourth-order active filter
Figure shows the effect of introducing such currents on the phase noise profile. It should be noted that the amount of offset current is crucial and hence further increases to its value might deteriorate the phase noise. This was observed in both measured and simulation in the presented platform. However, this comes at a hefty price in phase noise performance as will be illustrated in this section. Figure shows the lifting of the phase noise when a divide-by-4 prescaler is used to drive the multimodulus divider MMD.
Therefore, it is recommended to incorporate the prescaler within the main divider. This system was based on an implemented model platform constructed with a combination of measured raw data and behavioral Verilog-A models to speed up the simulation. Removing those nonlinearities shows the elimination of this phenomenon. Hence, this platform has enabled the reproduction of all witnessed behaviors in the laboratory of my first implemented synthesizer chip that showed unpredicted phenomenon at the time.
The platform presented in this chapter can help predict accurately the effect of nonlinearities of the frequency synthesizer subblocks on the overall performance. The developed platform has aided the design and successful implementation of the synthesizers presented in chapters 5 and 6, respectively. Perrott, M. Trott, and C. De Muer and M.
Filiol, T. Riley, C. Plett, and M. Effects of the different subblocks in the PLL on the entire phase noise of the closed-loop fractional-N synthesizer were monitored. Using a deep sub micron 0. Results obtained from measurements on this synthesizer outperform all synthesizers reported to date [1—6].
Figure shows the block diagram of a fractional-N frequency synthesizer. K Figure Fractional-N PLL Frequency Synthesizer Techniques to correct for those spurs include the use of analog compensation  using a digital-to-analogue converter, which injects an analog format of the error to cancel out the spurious signals. However, those analog techniques require great precision and matching, which is difficult to implement in practice rendering the counter measures insufficient to totally suppress the spurious signals within the band of interest.
The loop filter can therefore filter out the noise at those frequencies. In this chapter, the design and implementation of a complete fractional-N PLL frequency synthesizer is described in details. The synthesizer is designed using a commercial 0. A typical use of such a synthesizer is in the WLAN standard The synthesizer operates from a 1. The obtained performance is excellent and supersedes most published results in the WLAN arena. In what follows, the detailed design and implementation of the synthesizer is described. The specification of each individual subblock in the synthesizer is derived from the set of specifications shown in Table A scheme based on oscillator synthesis that generates two-thirds of the desired frequency mixed with a divided-by-2 version of it is employed for the This architecture is shown below in Figure As can be seen from Figure 5.
That was done to avoid frequency pulling in the transceiver . Proposed Synthesizer Architecture for Initial frequency planning is required for the employed oscillators derived from the required synthesized frequencies of interest for the VCO design is dictated by the specified phase noise requirement. Once the frequencies of the oscillators are selected, the current consumption for the front-end divide-by-2 prescalers is estimated.
The MMD architecture is determined based on its input frequency 1. The reference frequency of the crystal oscillator is chosen to be high 40 MHz to yield improved settling time and phase noise performance. However, it can not be too high to worsen the system performance see the 20 log10 N and a 10 log10 fsamp contributions to the phase noise plateau in Chapter 3. Once the VCO frequencies are selected, the limits for the required division ratios needed are obtained.
The simulation results obtained in chapter 4 aid the implementation of the proposed synthesizer architecture. The implementation and simulation of the individual subblocks of the PLL are described next. Figure shows the block diagram of the PFD. Since the delay of the reset can affect the PFD behavior in the vicinity of zero phase difference e. This circuit allows the choice between two modes of short and long delay in the reset line of the PFD. The delay in the reset path is used when operating the synthesizer in integer mode to get rid of the dead zone.
The delay is minimized when operating the synthesizer in fractional mode as the synthesizer operates at an offset of the dead zone. One of the main contributions to the phase noise from the PFD point of view is its inability to drive the CP switches at the required high sampling frequency associated with the fractional-N PLL. Figure shows the implemented PFD circuit using hand-crafted gates instead of the flip-flops to ensure the 72 Chapter 5 Figure In this section, a detailed circuit design for a CP is described. Several circuit simulations that characterize the CP are shown.
The schematic of this CP is shown in Figure Usually these UP and DN currents are mismatched and for higher tuning voltage at the loop filter, the UP current is smaller than the DN current and vice versa. A typical DC performance of a unit It is seen that ICP deviates from its horizontal zero net when the tuning voltage exceeds the 1. A residual mismatch helps suppress the spurious feed-through signals that modulate the VCO and appear at the output of the synthesizer. The mismatch cancellation technique shown in Figure is useful when the frequency synthesizer is operating in integer division mode.
However, as we will see later, this op-amp sensing cancellation technique is disabled when operating the synthesizer in fractional division mode. Those pulses get smaller due to the finite reset pulse which is the Figure Those pulses drive the CP switch transistors that have some time constants related to their input capacitances. Those switches cannot respond to small pulses and never fully switch ON depending on the speed of operation, hence the dead-zone effect.
The reference frequency used is 40 MHz. The dead-zone nonlinearity causes an increase in the in-band phase noise of the synthesizer due to the PFD not being able to correct for small errors creating a state where the loop keeps going into and out of lock all the time. The size of the dead-zone is proportional to the PFD sampling clock speed and therefore becomes 78 Chapter 5 more serious at higher frequency. Correcting this problem is very simple and requires the use of a longer reset pulse by putting a delay in front of the reset logic.
This issue arises if the feedback VCO frequency and the reference frequency at the PFD inputs are too different and their comparison phase error is too large and falls outside the range of the PFD. This problem can cause the PLL to cycle slip and hence increase its settling time. This can be resolved by extending the range of the PFD. This can degrade the performance of the PLL when used in the fractional-N mode because the input of the PFD in this mode is never zero; instead, it is a variable number with a zero mean. One way to avoid the issues around the zero is shifting the operating point away by adding some offset current.
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This, in fact, gives a systematic phase offset which is not important in a fractional synthesizer. Figure shows the schematic of the offset current circuit. The output current of this circuit is not an absolute value. Instead, it adds or subtracts a percentage of the CP current to the loop filter.
Therefore, it should have the same topology as the CP with some extra logic to control the offset current. As shown in the table of Figure 5. The table on the right-top corner of the figure summarizes the output current value based on control signals. Figure shows the CP blocks and their corresponding offset current circuit. The offset current is proportional to the total CP current. Figure shows the schematic of the simulation setup for the offset current and Figure shows the transient response of the offset current circuit.
In this simulation, the output short circuit current of the CP is measured. Figures — show the transient responses of the PFD and CP outputs for three different cases in which the two inputs a have almost the same phase, b the reference signal from the crystal is leading, and c the output of the divider in the PLL is leading. As it can be seen, there is always a positive glitch after the output is reset. The ring oscillator is simple and is typically constructed with multistage 86 Chapter 5 inverters.
The ring oscillator usually has worse phase noise performance  and is not suitable for high-performance design as the one presented in this chapter. The structure is fully differential as it offers better power supply rejection. Simplified Schematic of the Implemented Quadrature VCO The oscillator shown in Figure employs a bank of tunable varactors to cover the entire frequency range of interest for The oscillation is obtained for the described VCO and it is illustrated in Figure for the middle tuning range of 0.
These are the synthesized frequencies at point X in Figure The MMD circuit and system implementations are described in detail in Appendix D, however, its operation is shown briefly below: 90 Chapter 5 5. Counters decremented after rising edge of prescaler until counter A reaches 0. Counters are reset and cycle begins again. A step-by-step methodology is used from linear system model to actual hardware implementation.
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To establish the link between the model and the hardware implementation, its time domain behavior is first analyzed. The clock speed sampling clock at what the modulator can operate up to is critical. This is very important since the higher the clock of operation, the better is the noise shaping. However, since noise performance is critical in frequency synthesizers, the speed of operation forms a major part of the modulator design. Each accumulator is implemented using a bit pipelined adder. The resolution of the accumulator can easily be calculated using the frequency error allowed in the IEEE standards specification .
Figure 5. The bit pipelined adder is implemented using three-stage 8-bit carry look-ahead CLA adders to achieve very high clocking speed. Since at each CLA stage, the output is calculated during one clock cycle, the second-stage input is delayed one clock cycle and the thirdstage CLA input is delayed two clock cycles. The clocked delays synchronize the output of the CLA adders so that the output of the 24bit adder is arrives at the same time.
Equation 5. The correction is implemented by equally weighted differentiators. Expanding equation 5. Figure 96 Chapter 5 Table Divider Interface 5. The effect of these limit cycles is greatly reduced as we introduce dithering or randomness. Here, the spurs have been eliminated by introducing an error in the LSB or the input word . Previously, we introduced an error to remove any fractional spurs that may arise from limit cycles. It is advisable to bypass the noise shaper when selecting to operate in integer division in the synthesizer.
Figures and show the spectral densities of the modulator when the input is a DC with values of 0. It can be clearly seen that for both cases, the modulator exhibits lowfrequency spurs due to insufficient dither. This problem is rectified by effectively increasing the dither via the introduction of an initial seed  in the modulator as illustrated in Figure In what follows, we describe detailed performance of the implemented synthesizer and compare the obtained results with published performance of similar state-of-the-art synthesizers.
Figures and show a detailed block diagram and a photomicrograph of the fabricated synthesizer, respectively. It must be noted that this synthesizer was incorporated in an entire transceiver. The synthesizer performance was also monitored at the transmit node to show the effect of several anomalies of the RF section on the overall synthesizer performance. The entire chip is packaged in a pin micro-lead frame MLF and operates from a 1. They correlate pretty well with those simulated and shown in Figure Synthesizer Photomicrograph Chapter 5 Figure Adjacent 20 MHz-spaced channels are shown for the The MHz was measured with a 5 kHz resolution bandwidth whereas the MHz was measured with a Hz resolution bandwidth.
The frequency synthesizer achieves an integrated phase error of 0. This is illustrated in Figure The LO signal is monitored and FM demodulated while the receiver and transmitter are switched on and off, respectively. It is found that the LO signal settles to 2 ppm Figure Phase Noise Profile of the Synthesizer for Hence, an LO generation scheme that consists of a quadrature VCO operating at two-thirds of the LO frequency and a divide-by-2 circuit producing quadrature outputs at one-third of the LO frequency is employed.
The main challenge in the frequency synthesizer design for this multistandard transceiver lies in reducing the in-band phase noise while maintaining a fast loop locking time . Phase noise degrades signal EVM by introducing inter-subcarrier interferences. A narrower loop filter BW reduces out of band phase noise. If the loop filter BW is narrow and the loop takes too long to settle, frequency estimation in the baseband modem becomes inaccurate, thus degrading the total system performance. These two seemingly conflicting requirements can be fulfilled with the described fractionalN PLL.
The main advantage of a fractional-N PLL is that it breaks the traditional relationship between the channel spacing and the reference frequency in an integer-N PLL. By having a fractional divider, the reference frequency can be much higher, thus reducing the overall division ratio and in-band phase noise floor. Designed in a 0. A 4-bit A counter with a 3-bit B counter covers the required frequency range. As a noisy digital circuit, the modulator may generate substantial cross talk noise. Rategh 0. In essence, noise cross talk is avoided by time-domain isolation. As a conclusion, in this chapter, the author has detailed the design and performance of a multimode fractional-N synthesizer.
The synthesizer was designed as a local oscillator and constructed as part of a complete direct conversion transceiver. The measured results obtained for this synthesizer supersede most published results see Table The developed platform of chapter 4 has helped the designed synthesizer in achieving the best performance to date. In chapter 6, we propose a new adaptive and enhanced synthesizer architecture that offers optimum performance.
De Muer, M. Shu, Ka Lok Lee, B. Zhang, T. Nguyen, C. Gambetta, T. Soorapanth, B. Zhang, L. Der, D. Guo, I. Goldberg, Sciteq Electronics Inc. Rohde, Synergy Microwave Corp. Verma, J. Xu, and T. Chiu, Y. Chen, and S. Bourdi, et al. The synthesizer offered the best performance to date. However, additional circuit could be designed to enhance the performance of the synthesizer at the cost of increased circuit complexity. Those additions include adaptive CP architecture to maintain loop gain and phase transfer functions while operating in fractional mode, i. Also included is an adaptive band switching control to maintain frequency agility while offering optimum phase noise performance in the band of interest.
Along with other additional techniques that improve the synthesizer performance, those additions will be described in this chapter in detail. Several circuit techniques could be added to this synthesizer architecture to enhance its performance. Fractional-N Synthesizer with Enhanced Performance Improved Performance Fractional-N Frequency Synthesizer Those circuit improvements are shown in Figure using the dashed blocks and lines and are identified as follows: 1.
VCO gain calibration to maintain best loop dynamics for best phase noise performance 3. Each one of those is described in detail in the next few pages and measured results based on all these joint techniques applied to the synthesizer are shown at the end of the chapter. Until recently [1—5], the use of noise shaping has been limited to fractional divider control.
These instantaneous divider variations continuously alter the PLL loop dynamics and deteriorate phase noise performance. In what follows, we will describe a new fractional-N synthesizer architecture based on an adaptive CP that was fully implemented in an RF CMOS process and show measured phase noise results that satisfy several system requirements. This alters the loop dynamics that impact the phase noise performance. It also has direct influence on the PLL open loop dynamics, as is proven in the following derivation.
Closed Loop Gain dB 3. Closed-Loop Gain and Phase Characteristics The example given here illustrates a typical system and clearly shows the gain and phase variations during the synthesis of the middle frequency band. Manipulating equations 6.
Notice that since Ninst changes according to equation 6. The new closed-loop equation for the proposed architecture would then be given by equation 6. The coding method employed on the b bits is thermometer coding as used in current-segmented digital-to-analog converters . Adaptive Charge Pump Architecture 6. The loop gain affects the loop bandwidth, phase noise performance, and predistortion matching.
Equation 3. In a multimode PLL frequency synthesizer, the integrated loop filter pole and zero locations, vary greatly from frequency to frequency, as well as with process. The pole and zero locations are determined by the loop filter RC time constant. This will make sure exceeding or at least meeting those specifications after the final calibration is done. Starting from the previously defined loop gain in chapter 3 as shown in equation 3.
N divider variations have been taken care of in section 6. The VCO gain is designed to be within a well-determined window that can meet the specified performance criteria at nominal and hence will not be calibrated directly. Hence, the CP current are the only elements of the loop that will be calibrated. Therefore, we do not need to program the capacitance, C, and only need to calibrate the CP current and the resistor R to account for all five PLL loop elements variations.
Rearranging equations 6. K VCO. Rnom Cnom. Looking at the above equations, we can see that the CP current need to adjust for three sources of errors in the loop. ROi provides solutions that focus on building business by developing people. Our innovative E. Training System Your download cmos single chip fast frequency hopping of the option and shares happens many to these pages and components.
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